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CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
1CY7C025/0251
CY7C09269V/79V/89V CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous access of the same memory location * 6 Flow-Through/Pipelined devices -- 16K x 16/18 organization (CY7C09269V/369V) -- 32K x 16/18 organization (CY7C09279V/379V) -- 64K x 16/18 organization (CY7C09289V/389V) * 3 Modes -- Flow-Through -- Pipelined -- Burst * Pipelined output mode on both ports allows fast 100-MHz operation * 0.35-micron CMOS for optimum speed/power * High-speed clock to data access 6.5[1, 2]/7.5[2]/9/12 ns (max.) * 3.3V low operating power -- Active = 115 mA (typical) -- Standby = 10 A (typical) * Fully synchronous interface for easier operation * Burst counters increment addresses internally -- Shorten cycle times -- Minimize bus noise -- Supported in Flow-Through and Pipelined modes * Dual Chip Enables for easy depth expansion * Upper and Lower Byte Controls for Bus Matching * Automatic power-down * Commercial and Industrial temperature ranges * Pb-Free 100-pin TQFP Package Available
Logic Block Diagram
R/WL UBL R/WR UBR
CE0L CE1L LBL OEL
1
0/1
1
0/1
0
0
CE0R CE1R LBR OER
FT/PipeL I/O8/9L-I/O15/17L I/O0L-I/O7/8L
[5] A0L-A13/14/15L [4]
8/9 14/15/16
0/1
1b 0b 1a 0a
b a
0a 1a 0b 1b
a b
0/1
FT/PipeR
8/9
[3]
8/9
I/O Control
I/O Control
I/O8/9R-I/O15/17R
8/9 14/15/16
[3]
I/O0R-I/O7/8R
[5] A0R-A13/14/15R
[4]
CLKL ADSL CNTENL CNTRSTL
Counter/ Address Register Decode
True Dual-Ported RAM Array
Counter/ Address Register Decode
CLKR ADSR CNTENR CNTRSTR
Notes: 1. Call for availability. 2. See page 6 for Load Conditions. 3. I/O8-I/O15 for x16 devices; I/O9-I/O17 for x18 devices. 4. I/O0-I/O7 for x16 devices. I/O0-I/O8 for x18 devices. 5. A0-A13 for 16K; A0-A14 for 32K; A0-A15 for 64K devices.
Cypress Semiconductor Corporation Document #: 38-06056 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 Revised April 6, 2005
CY7C09269V/79V/89V CY7C09369V/79V/89V
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[6] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1, 2] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs. Counter enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter will increment on each LOW to HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND A0R A1R A2R A3R A4R A5R A6R A7R A8R A8L A7L A6L A5L A4L A3L A2L A1L A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A9R A10R A11R A12R A13R A14R A15R NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER FT/PIPER GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
[7] A14L [8] A15L
NC NC LBL UBL CE0L CE1L CNTRSTL VCC R/WL OEL
[7] [8]
CY7C09289V (64K x 16) CY7C09279V (32K x 16) CY7C09269V (16K x 16)
[9] FT/PIPEL
GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
[9]
I/O0R
I/01R
GND
GND
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
VCC
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Notes: 6. When writing simultaneously to the same location, the final value cannot be guaranteed. 7. This pin is NC for CY7C09269V. 8. This pin is NC for CY7C09269V and CY7C09279V. 9. For CY7C09269V and CY7C09279V, pin #18 connected to VCC is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin compatible to an IDT 5V x16 flow-through device.
Document #: 38-06056 Rev. *B
I/O0L
NC
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Pin Configurations (continued)
100-Pin TQFP (Top View)
CNTENR CNTENL ADSR CLKR ADSL CLKL GND GND A0R A1R A2R A3R A4R A5R A6R A7R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A8L A7L A6L A5L A4L A3L A2L A1L A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L A10L A11L A12L A13L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A8R A9R A10R A11R A12R A13R A14R A15R LBR UBR CE0R CE1R CNTRSTR R/WR GND OER FT/PIPER I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
[10]A14L [11]A15L
LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC FT/PIPEL I/O17L I/O16L GND I/O15L I/O14L I/O13L 1/012L I/O11L I/O10L
[10] [11]
CY7C09389V (64K x 18) CY7C09379V (32K x 18) CY7C09369V (16K x 18)
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
GND
GND
I/01R
Selection Guide
CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V -6[1, 2] -7[2] -9 -12 fMAX2 (MHz) (Pipelined) Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current ICC (mA) Typical Standby Current for ISB1 (mA) (Both Ports TTL Level) Typical Standby Current for ISB3 (A) (Both Ports CMOS Level) 100 6.5 83 7.5 67 9 50 12
175 25
155 25
135 20
I/10R
VCC
VCC
115 20
10 A
10 A
10 A
10 A
Notes: 10. This pin is NC for CY7C09369V. 11. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Pin Definitions
Left Port A0L-A15L ADSL Right Port A0R-A15R ADSR Description Address Inputs (A0-A14 for 32K, A0-A13 for 16K devices). Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins. Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 VIL and CE1 VIH). Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX. Counter Enable Input. Asserting this signal LOW increments the burst address counter of its respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted LOW. Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN. Data Bus Input/Output (I/O0-I/O15 for x16 devices). Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the lower byte. (I/O0-I/O8 for x18, I/O0-I/O7 for x16) of the memory array. For read operations both the LB and OE signals must be asserted to drive output data on the lower byte of the data pins. Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L-I/O15/17L). Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations. Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH. Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For pipelined mode operation, assert this pin HIGH. Ground Input. No Connect. Power Input. Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >1100V Latch-Up Current...................................................... >200mA
CE0L,CE1L CLKL CNTENL
CE0R,CE1R CLKR CNTENR
CNTRSTL I/O0L-I/O17L LBL
CNTRSTR I/O0R-I/O17R LBR
UBL OEL R/WL FT/PIPEL GND NC VCC
UBR OER R/WR
FT/PIPER
Maximum Ratings[12]
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State............................-0.5V to VCC+0.5V DC Input Voltage......................................-0.5V to VCC+0.5V
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 300 mV 3.3V 300 mV
Note: 12. The voltage on any input or I/O pin can not exceed the power pin during power-up.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Electrical Characteristics Over the Operating Range
CY7C09269V/79V/89V CY7C09369V/79V/89V -6[1, 2] Max. Min. Min. Typ. Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage (VCC = Min. lOH = -4.0 mA) Output LOW Voltage (VCC = Min. lOH = +4.0 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current Operating Current (VCC = Max, IOUT = 0 mA) Outputs Disabled Com'l. Indust. 25 95 -10 2.0 0.8 10 175 320 -10 -7[2] Max. Min. Typ. -9 Max. Min. Typ. -12 Max. 0.4 2.0 0.8 -10 135 185 20 35 95 105 10 10 85 95 10 230 300 75 85 155 165 250 250 115 125 75 10 250 85 20 70 -10 115 0.8 10 Unit pF pF Typ. Unit V V V V A mA mA mA 140 mA mA A A 100 mA mA
2.4 0.4
2.4 0.4 2.0 0.8 10 155 275 275 390 25 85 115 175 85 120
2.4 0.4 2.0
2.4
180 mA
Standby Current (Both Com'l. Ports TTL Level)[13] CEL & Indust. CER VIH, f = fMAX Standby Current (One Port Com'l. TTL Level)[13] CEL | CER Indust. VIH, f = fMAX Standby Current (Both Com'l. Ports CMOS Level)[13] CEL Indust. & CER VCC - 0.2V, f = 0 Standby Current (One Port Com'l. CMOS Level)[13] CEL | CER Indust. VIH, f = fMAX
105 165 165 210
10
250
10 10
250 250 125
105 135
95
125 170
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 10 10
Note: 13. CEL and CER are internal signals. To select either the left or right port, both CE0 and CE1 must be asserted to their active states (CE0 VIL and CE1 VIH).
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
AC Test Loads
3.3V 3.3V R1 = 590 OUTPUT C = 30 pF R2 = 435 OUTPUT C = 30 pF VTH = 1.4V RTH = 250 R1 = 590 OUTPUT C = 5 pF R2 = 435
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1)
(c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig)
AC Test Loads (Applicable to -6 and -7 only)[14]
OUTPUT C
Z0 = 50
R = 50 3.0V GND VTH = 1.4V 10% 3 ns
ALL INPUT PULSES
90% 90% 10% 3 ns
(a) Load 1 (-6 and -7 only)
0. 60
0. 50
(ns) for all -7 access times
0. 40
0. 30
0. 20
0. 1 0
0. 00 10 15 20 25 30 35
Capacitance (pF)
(b) Load Derating Curve
Note: 14. Test Conditions: C = 10 pF.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Characteristics Over the Operating Range
CY7C09269V/79V/89V CY7C09369V/79V/89V -6[1, 2] Max. Min. Parameter fMAX1 fMAX2 tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ[15,16] tOHZ[15,16] tCD1 tCD2 tDC tCKZ tCKZ
[15,16] [15,16]
-7[2] Max. Min.
-9 Max. Min.
-12 Max. 33 50 30 20 12 12 8 8 3 3 3 3 4 1 4 1 4 1 4 1 4 1 5 1 4 1 10 12 2 7 20 9 1 7 25 12 2 9 2 2 40 15 40 15 9 Min. Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description fMax Flow-Through fMax Pipelined Clock Cycle Time - Flow-Through Clock Cycle Time - Pipelined Clock HIGH Time - Flow-Through Clock LOW Time - Flow-Through Clock HIGH Time - Pipelined Clock LOW Time - Pipelined Clock Rise Time Clock Fall Time Address Set-Up Time Address Hold Time Chip Enable Set-Up Time Chip Enable Hold Time R/W Set-Up Time R/W Hold Time Input Data Set-Up Time Input Data Hold Time ADS Set-Up Time ADS Hold Time CNTEN Set-Up Time CNTEN Hold Time CNTRST Set-Up Time CNTRST Hold Time Output Enable to Data Valid OE to Low Z OE to High Z Clock to Data Valid - Flow-Through Clock to Data Valid - Pipelined Data Output Hold After Clock HIGH Clock HIGH to Output High Z Clock HIGH to Output Low Z Write Port Clock HIGH to Read Data Delay Clock to Clock Set-Up Time
53 100 19 10 6.5 6.5 4 4 3 3 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 8 2 1 7 15 6.5 2 2 2 30 9 9 2 2 2 2 1 4 0 4 0 4 0 4 0 4 0 4.5 0 4 0 22 12 7.5 7.5 5 5
45 83 25 15 12 12 6 6 3 3 4 1 4 1 4 1 4 1 4 1 5 1 4 1 9 2 7 18 7.5 2 9 2 2 35 10 1
40 67
Port to Port Delays tCWDD tCCS
Notes: 15. Test conditions used are Load 2. 16. This parameter is guaranteed by design, but it is not production tested.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[17, 18, 19, 20]
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tHC tSC tHC
R/W
tSW tSA An
tHW tHA An+1 tCD1 tDC Qn tCKLZ Qn+1 tOHZ tOLZ tDC An+2 An+3 tCKHZ Qn+2
ADDRESS DATAOUT
OE tOE
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[17, 18, 19, 20]
tCH2 CLK tCYC2 tCL2
CE0 tSC CE1 tHC tSC tHC
R/W tSW tSA ADDRESS DATAOUT An 1 Latency tHW tHA An+1 tCD2 Qn tCKLZ OE
tOE Notes: 17. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 18. ADS = VIL, CNTEN and CNTRST = VIH. 19. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock. 20. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
An+2 tDC Qn+1 tOHZ
An+3
Qn+2 tOLZ
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Bank Select Pipelined Read[21, 22]
tCH2 CLKL tSA ADDRESS(B1) tSC CE0(B1) tCD2 DATAOUT(B1) tSA ADDRESS(B2) A0 tHA A1 tSC CE0(B2) tSC DATAOUT(B2) tCKLZ tHC tCD2 D2 tCKLZ tCKHZ tCD2 D4 tSC D0 tDC A2 tHC tHC tCD2 D1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 D3 tCKHZ A0 tHC tHA A1 A2 A3 A4 A5 tCYC2 tCL2
Left Port Write to Flow-Through Right Port Read[23, 24, 25, 26]
CLKL R/WL tSA ADDRESSL tSD DATAINL CLKR R/WR ADDRESSR tSW tSA tHW tHA NO MATCH tCWDD DATAOUTR tDC VALID tDC tCD1 VALID VALID tCCS tCD1 MATCH tHD tHA NO MATCH
tSW
tHW
MATCH
Notes: 21. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1) = ADDRESS(B2). 22. UB, LB, OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 23. The same waveforms apply for a right port write to flow-through left port read. 24. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 25. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 26. It tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid until tCCS + tCD1. tCWDD does not apply in this case.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Pipelined Read-to-Write-to-Read (OE = VIL)[20, 27, 28, 29]
tCH2 CLK tCYC2 tCL2
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN An tHA tCD2 Qn READ NO OPERATION WRITE READ tCKHZ tHW An+1 An+2 An+2 tSD tHD Dn+2 tCKLZ tCD2 Qn+3 An+3 An+4 tHW tHC
DATAOUT
Pipelined Read-to-Write-to-Read (OE
tCH2 CLK tCYC2 tCL2
Controlled)[20, 27, 28, 29]
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW An tSA
tHW An+1 tHA tCD2 An+2 tSD tHD Dn+2 Dn+3 tCKLZ Qn tOHZ tCD2 Qn+4 An+3 An+4 An+5
ADDRESS DATAIN
DATAOUT
OE READ WRITE READ
Notes: 27. Output state (High, LOW, or high impedance) is determined by the previous cycle control signals. 28. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 29. During "No Operation", data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Flow-Through Read-to-Write-to-Read (OE = VIL)[18, 20, 28, 29]
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN DATAOUT tCD1 Qn tDC READ An tHA tCD1 Qn+1 tCKHZ NO OPERATION tCKLZ WRITE tHW An+1 An+2 tSD Dn+2 tCD1 Qn+3 tDC READ tCD1 An+2 tHD An+3 An+4 tHW tHC
Flow-Through Read-to-Write-to-Read (OE Controlled)[18, 20, 27, 28, 29]
tCH1 CLK tCYC1 tCL1
CE0 tSC CE1 tSW R/W tSW ADDRESS tSA DATAIN DATAOUT OE READ WRITE READ tCD1 Qn tOHZ tCKLZ An tHA tDC tHW An+1 tSD Dn+2 An+2 tHD Dn+3 tOE tCD1 Qn+4 tDC tCD1 An+3 An+4 An+5 tHW tHC
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Pipelined Read with Address Counter Advance[30]
tCH2 CLK tSA ADDRESS tSAD ADS tSAD CNTEN tSCN DATAOUT Qx-1 READ EXTERNAL ADDRESS tHCN Qx tDC tCD2 Qn READ WITH COUNTER tSCN Qn+1 COUNTER HOLD tHCN Qn+2 Qn+3 tHAD An tHAD tHA tCYC2 tCL2
READ WITH COUNTER
Flow-Through Read with Address Counter Advance[30]
tCH1 CLK tSA ADDRESS tSAD ADS tSAD CNTEN tSCN tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn Qn+1 Qn+2 tSCN tHCN tHAD An tHAD tHA tCYC1 tCL1
DATAOUT
Qn+3 READ WITH COUNTER
READ WITH COUNTER
COUNTER HOLD
Note: 30. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[31, 32]
tCH2 CLK tSA ADDRESS An tHA tCYC2 tCL2
INTERNAL ADDRESS tSAD ADS tHAD
An
An+1
An+2
An+3
An+4
CNTEN tSCN DATAIN tSD Dn tHD WRITE EXTERNAL ADDRESS tHCN Dn+1 WRITE WITH COUNTER Dn+1 Dn+2 Dn+3 Dn+4
WRITE COUNTER HOLD
WRITE WITH COUNTER
Notes: 31. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 32. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Switching Waveforms (continued)
Counter Reset (Pipelined Outputs)[20, 27, 33, 34]
tCH2 CLK tSA ADDRESS INTERNAL ADDRESS R/W tSAD ADS tSCN CNTEN tSRST CNTRST DATAIN DATAOUT COUNTER RESET WRITE ADDRESS 0 READ ADDRESS 0 tHRST tSD D0 Q0 READ ADDRESS 1 Q1 READ ADDRESS n Qn tHD tHCN tHAD AX tSW tHW 0 1 An An tHA An+1 An+1 tCYC2 tCL2
Notes: 33. CE0, UB, and LB = VIL; CE1 = VIH. 34. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Read/Write and Enable Operation[35, 36, 37]
Inputs OE X X X L H X CLK CE0 H X L L L CE1 X L H H H R/W X X L H X Outputs I/O0-I/O17 High-Z High-Z DIN DOUT High-Z Deselected Operation
[38]
Deselected[38] Write Read[35] Outputs Disabled
Address Counter Control Operation[35, 39, 40, 41]
Address X An X X Previous Address X X An An CLK ADS X L H H CNTEN X X H L CNTRST L H H H I/O Dout(0) Dout(n) Dout(n) Dout(n+1) Mode Reset Load Hold Increment Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked--Counter Disabled Counter Enabled--Internal Address Generation
Notes: 35. "X" = "Don't Care", "H" = VIH, "L" = VIL. 36. ADS, CNTEN, CNTRST = "Don't Care". 37. OE is an asynchronous input signal. 38. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle. 39. CE0 and OE = VIL; CE1 and R/W = VIH. 40. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle. 41. Counter operation is independent of CE0 and CE1.
Document #: 38-06056 Rev. *B
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CY7C09269V/79V/89V CY7C09369V/79V/89V
Ordering Information
16K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 Ordering Code CY7C09269V-6AC CY7C09269V-6AXC CY7C09269V-7AC CY7C09269V-7AXC CY7C09269V-9AC CY7C09269V-9AXC CY7C09269V-9AI 12 CY7C09269V-12AC CY7C09269V-12AXC 32K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09279V-6AC CY7C09279V-6AXC CY7C09279V-7AC CY7C09279V-7AXC CY7C09279V-9AC CY7C09279V-9AI CY7C09279V-12AC CY7C09279V-12AXC 64K x16 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 Ordering Code CY7C09289V-6AC CY7C09289V-6AXC CY7C09289V-7AC CY7C09289V-7AXC CY7C09289V-9AC CY7C09289V-9AXC CY7C09289V-9AI CY7C09289V-9AXI 12 CY7C09289V-12AC CY7c09289V-12AXC Package Name A100 A100 A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Package Name A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Industrial Commercial Commercial Package Name A100 A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Industrial Commercial Commercial
Document #: 38-06056 Rev. *B
Page 16 of 19
CY7C09269V/79V/89V CY7C09369V/79V/89V
16K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5
[1, 2]
Ordering Code CY7C09369V-6AC CY7C09369V-6AXC CY7C09369V-7AC CY7C09269V-7AXC CY7C09369V-7AI
Package Name A100 A100 A100 A100 A100 A100 A100 A100 A100 A100
Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack
Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Commercial Industrial Commercial Commercial
7.5
[2]
9
CY7C09369V-9AC CY7C09369V-9AXC CY7C09369V-9AI
12
CY7C09369V-12AC CY7C09369V-12AXC
32K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 12 Ordering Code CY7C09379V-6AC CY7C09379V-6AXC CY7C09379V-7AC CY7C09379V-9AC CY7C09379V-9AI CY7C09379V-12AC CY7C09379V-12AXC 64K x18 3.3V Synchronous Dual-Port SRAM Speed (ns) 6.5[1, 2] 7.5[2] 9 Ordering Code CY7C09389V-6AC CY7C09389V-6AXC CY7C09389V-7AC CY7C09389v-7AXC CY7C09389V-9AC CY7C09389V-9AXC CY7C09389V-9AI CY7C09389V-9AXI 12 CY7C09389V-12AC CY7C09389V-12AXC Package Name A100 A100 A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Commercial Commercial Package Name A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Pb-Free Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Commercial
Document #: 38-06056 Rev. *B
Page 17 of 19
CY7C09269V/79V/89V CY7C09369V/79V/89V
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06056 Rev. *B
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C09269V/79V/89V CY7C09369V/79V/89V
Document History Page
Document Title: CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K X 16/18 Synchronous Dual Port Static RAM Document Number: 38-06056 REV. ** *A *B ECN NO. 110215 122306 344354 Issue Date 12/18/01 12/27/02 See ECN Orig. of Change SZV RBI PCX Description of Change Change from Spec number: 38-00668 to 38-06056 Power up requirements added to Maximum Ratings Information Added Pb-Free Part Ordering Information
Document #: 38-06056 Rev. *B
Page 19 of 19

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